1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device having a capacitor structure in which a capacitor film made of a ferroelectric material is sandwiched between a lower electrode and an upper electrode.
2. Description of the Related Art
As a nonvolatile memory capable of storing information even when a power supply is stopped, a flash memory and an FRAM (Ferro-electric Random Access Memory, a registered trade mark of Ramtron International Corporation, U.S.A.) are known.
The flash memory has a floating gate embedded in a gate insulating film of an IGFET (Insulated Gate Field Effect Transistor), and stores information by accumulating electric charges indicating storage information in the floating gate. In order to write/delete information, it is necessary to flow a tunnel current passing through the insulating film, and so a relatively high voltage is required.
On the other hand, the FRAM stores information using a hysteresis characteristic of a ferroelectric. A ferroelectric capacitor structure, which has a ferroelectric film as a capacitor dielectric between a pair of electrodes, generates a polarization in response to an applied voltage between the electrodes, and has a spontaneous polarization even when the applied voltage is removed. When a polarity of the applied voltage is reversed, a polarity of the spontaneous polarization is also reversed. Detection of this spontaneous polarization enables reading of information. The FRAM operates at a lower voltage compared with the flash memory, and high-speed writing is possible with saved power.
FIG. 12A is a circuit diagram of a 2T/2C type memory cell of the FRAM. In FIG. 12A, there is shown the 2T/2C type memory cell in which two transistors Ta, Tb and two capacitors Ca, Cb are used for storing one bit information. In such a 2T/2C type memory cell, a complementary operation is carried out in which information of “1” or “0” is stored in one capacitor Ca, while reverse information is stored in the other capacitor Cb. Meanwhile, though the 2T/2C type memory cell has a configuration resistant to variation of processes, the 2T/2C type memory cell has a cell area of approximately twice a memory cell area of a 1T/1C type memory cell described below.
FIG. 12B is a circuit diagram of the 1T/1C type memory cell of the FRAM. In FIG. 2B, there is shown the 1T/1C type memory cell in which one transistor T1 and one capacitor C1 can be used or the other transistor T2 and the other capacitor C2 can be used for storing one bit information, and a configuration thereof is similar to that of a DRAM. Such a 1T/1C type memory cell has a small cell area and is capable of high integration. However, a reference voltage is required in order to judge whether an electric charge read from the memory cell is information of “0” or information of “1”. A reference cell generating this reference voltage reverses the polarization every time the electric charge is read. Therefore, the reference cell deteriorates faster than the memory cell due to fatigue. Additionally, the 1T/1C type has a narrower margin of judgment than the 2T/2C type, and is vulnerable to variation of processes.
As capacitor films of the capacitors in FIG. 12A and FIG. 12B, there are used a material of PZT series such as PZT (Pb(Zr, Ti)O3), La-doped PZT (PLZT) or the like, or a Bi-layered structure compound such as SBT (SrBi2Ta2O9), SBTN (SrBi2(Ta, NB)2O9) or the like, being a ferroelectric film. These ferroelectric films are easy to be reduced by hydrogen, and in order to maintain quality as a FRAM, it is necessary to carry out a recovery annealing in an oxidizing atmosphere of 500° C. to 700° C. after the ferroelectric film is formed. It is because a process after formation of a ferroelectric capacitor structure such as growth of an interlayer insulating film includes a step in which hydrogen is generated.
There is a tendency that the 1T/1C type circuit enabling high integration is used and a stacked type FRAM (structure in which the ferroelectric capacitor structure and a selection transistor structure are directly connected with a conductive plug) is adopted in order to further improve integration degree, as a FRAM of the next generation, for example a FRAM of 0.18 μm generation.
As a material for the conductive plug connected to the ferroelectric capacitor structure in the stacked type FRAM, tungsten (W) is generally used. It is because tungsten (W) has a lower resistance a heat resistance, compared with polycrystalline silicon to which an impurity is added. However, since tungsten (W) becomes an oxide with an extremely high resistance when oxidized, the resistance becomes high even when a part thereof is oxidized and it becomes hard to secure contact.
On the other hand, for a lower electrode of the ferroelectric capacitor structure, a noble metal such as platinum (Pt) or iridium (Ir) is used in order to evade oxidation deterioration due to the above-described recovery annealing in the oxidizing atmosphere. Additionally, there is also used a conductive noble metal oxide which can maintain conductivity even when oxidized, for example, IrO2, SrRuO3, La0.5Sr0.5CoO3 or the like.
However, the lower electrode made of the material as above cannot restrain diffusion of oxygen at a temperature of about 600° C. Therefore, if the recovery annealing is carried out at the high temperature as above, a W plug in the stacked type FRAM is oxidized through the lower electrode.
In order to prevent such oxidation, it is suggested that an oxygen barrier layer is provided between the lower electrode and the conductive plug (see Patent Document 1, for example). In this suggestion, it is reported that a titanium aluminum nitride (TiAlN) film to be the oxygen barrier layer is inserted between a titanium nitride (TiN) film being a part of the conductive plug and the lower electrode. If such an oxygen barrier layer is provided, oxidation of the conductive plug can be prevented. It is because an oxidation speed of TiAlN is slower than that of TiN by more than two digits. Though aluminum nitride (AlN) itself exhibits insulation performance, aluminum nitride (AlN) exhibits conductivity when a cation impurity such as titanium (Ti) is added or an AlN film which is deficient in nitride (N) is formed, and therefore contact failure by providing this oxygen barrier does not become a problem.
As methods for forming the ferroelectric film to be the capacitor film, in addition to a sputtering method, there are presently known a sol-gel method and an MOCVD (Metal Organic Chemical Vapor Deposition) method. When the ferroelectric film, for example a PZT film, is formed by the sputtering method, platinum (Pt) is used as the material for the lower electrode to be a base thereof. It is because the lower electrode to be the base of the PZT film is required to be intensely oriented to the (111) face in order to increase the spontaneous polarization of a crystal of the PZT film, and platinum (Pt) is suitable as the base of the PZT film since platinum is intensely oriented to the (111) face.
However, the PZT film made by the sputtering method is poor in crystallinity if it is formed at a high temperature. Therefore, it is necessary that, after an amorphous film is formed at a low temperature, a rapid thermal annealing (RTA) is carried out in an oxygen atmosphere for crystallization. Since crystallization by the RTA processing requires a high temperature of 700° C. or more, it is afraid that the W plug is oxidized in the stacked type FRAM even if the oxygen barrier layer such as TiAlN is used.
In contrast, when the PZT film is formed by the MOCVD method, the PZT film is grown with good crystallinity being maintained on the lower electrode in a growth process. Therefore, a crystallization annealing is unnecessary and the lowering of the temperature in the process can be expected.
However, when the PZT film is formed by the MOCVD method, platinum (Pt) is unsuitable as a composing material of the lower electrode. It is because lead (Pb) in the PZT film reacts with platinum (Pt) and forms PtPbx, and roughness is generated on an interface between the lower electrode and the PZT film, deteriorating film quality. Therefore, when the PZT film is formed by the MOCVD method, a material other than platinum (Pt) must be selected as the lower electrode.
Thus, when forming the ferroelectric film by the MOCVD method, it is necessary to adopt a noble metal other than platinum (Pt) or a conductive noble metal oxide as the lower electrode. Among such materials, if an oxide conductive material such as iridium oxide (IrOx) is used as the lower electrode, the oxide conductive material is reduced at the time of formation of the PZT film by the MOCVD method, and so it is difficult to adopt the oxide conductive material. Therefore, the noble metal such as iridium (Ir) is adopted as the material for the lower electrode.
If the TiAlN film as the oxygen barrier layer is also used when the noble metal such as iridium (Ir) is used as the material of the lower electrode as above, contact capability of the W plug can be maintained even if the recovery annealing is carried out at 700° C. Therefore, insertion of the TiAlN film is advantageous in terms of oxidation resistance of the W plug.
[Patent Document 1] Japanese Patent Application Laid-open No. Hei 8-64786
As described above, in adopting the stacked type structure to enhance further miniaturization and high integration in the FRAM, various contrivances are made about oxidation prevention of the W plug connected to the lower electrode in the ferroelectric capacitor structure, selection of the ferroelectric material for obtaining a superior orientation property of the ferroelectric film to be the capacitor film, and preferable selection of the lower electrode material considering the ferroelectric material which is superior in oxidation prevention of the W plug and the orientation property, and careful consideration is given in order to solve inconveniences occurring when the respective configurations are adopted.
Further, in the stacked type FRAM, in order to realize high integration thereof substantially, it is fundamental that a multi-layered body of the respective films (lower electrode film, capacitor film and upper electrode film) constituting the ferroelectric capacitor structure is collectively etched (one mask etching process) at the time of formation of the ferroelectric capacitor structure.